A sub-ranging analog to digital converter (ADC) uses a resistor ladder and an array of comparators in order to quantize an input voltage to a series of bits. The bits are then latched to a held value and sent to a digital to analog converter (DAC) in order to subtract the quantized value from the input voltage, resulting in a residual voltage which is quantized at a finer value at a subsequent quantizing stage in the sub-ranging ADC.
FIG. 1 is a schematic block diagram illustrating a sub-ranging ADC architecture 100. In a typical sub-ranging ADC architecture, a series of pipeline connected ADC/DAC pairs (labeled in stages a and b) are used to convert a corresponding portion of the analog input signal 101. Each ADC/DAC pair utilizes ADC 120 to generate a digital value that is provided to encoder 140. Referring to the architecture shown in FIG. 1, sample and hold circuit 110 samples the analog input signal 101 and stores the sampled voltage values. The voltage samples are input to ADC 120. ADC 120 converts the sampled voltage levels to a digital sample value in encoder 140. The sub-ranging ADC architecture 100 comprises a number of pipelined stages, where each stage includes a quantizer 130. Quantizer 130 includes an ADC 120, encoder 140 and a DAC 150. Each quantizer 130 processes a portion of the digital output signal. For example, each quantizer 130 may encode a given number of bits of the final digital output. The portion of the signal encoded by the quantizer 130 is converted back to an analog signal by DAC 150. The analog output signal 151 is subtracted from the previous stage's input signal 111 output from DAC 150 via summing circuit 160. The stage a output 161 is further processed in similar manner by second sample and hold 110 (stage b) and second ADC 120 and second DAC 150 with the digital output being provided by second encoder 140. The resulting net output signal (e.g. residual signal 161) is processed by the subsequent quantizer stage to produce the next portion of the digital output signal for the sub-ranging ADC 100. Thus, the output signal 161 of a previous quantizer stage serves to provide the input for the next quantizer stage defining a pipelined process. This pipelined process continues over each quantizing stage until all portions of the initial input signal have been converted to digital signals. The resulting digital outputs of the quantizing stages are combined to form the final digital output.
ADC 120 may be a flash (or parallel) ADC 120 which includes a resistor ladder 122 and a comparator 126 associated with each resistor 123 in the resistor ladder 122. The input signal voltage 121 crosses each resistor 123 in resistor ladder 122, and the associated comparator 126 determines whether the input signal voltage is higher (or lower) than the voltage across resistors 123 determined by a reference current flowing through resistor ladder 122. The comparators 126 output a zero or one value to indicate whether or not the input signal voltage 121 value exceeds the voltage level for a corresponding resistor 123. The comparator output is sent to a latch 127 to control the time at which the output values from the comparators may change. The output data 128 is then output from the latches 127 and output to the encoder 140 and the DAC 150 of the quantizer 130 stage.
As the quantized value is being held in the latch circuit 127, the input voltage 121 may change and cause one or more of the comparators 126 to flip the value of their output bits. This change in comparator output value may create glitches which feed through the latch circuit 127 in the form of input feed-through, which degrades the residual voltage value and degrades performance of the sub-ranging ADC.
These glitches are illustrated with reference to FIG. 2A through FIG. 2D. FIG. 2A shows the ADC 120 of FIG. 1 depicting analog input signal 121, and resistor ladder 122 which provides voltage signals to comparators 126. Comparators 126 produce digital output signals which are input to latch circuits 127. The latched bits from comparators 126 are provided as output bits 128, after which latch circuits 127 may be unlatched to receive the next series of digital outputs from comparators 126. FIG. 2B, FIG. 2C and FIG. 2D are graphical depictions of the input signal voltage, the comparator outputs and the ADC output signal, respectively, as a function of time 210. FIGS. 2B, 2C and 2D illustrate a common time interval along their horizontal axes 210. Referring to FIG. 2D, latch circuits 127 are placed in a latched state at time Tlatch 220. At time T0 218, the input signal 121, shown in FIG. 2B, changes from a first voltage level 230 to a second voltage level 231. At T0, the latch circuits 127 are latched and the output of latches 127 should not change despite the change in input voltage 121 at T0. However, as the input voltage 121 changes, comparators 126 are provided the new voltage levels from resistor ladder 122, which may cause some of the comparator outputs to flip. As shown in FIG. 2C, comparator outputs 240 and 241 flip to a low state, while comparator outputs 242 and 243 remain high at T0. These state changes in the comparator outputs are fed through to the latched latch circuits 127 and cause perturbations or glitches in the latch output, shown at T0 in FIG. 2D denoted as 250.
Glitches caused by input feed-through create degradation in performance that either must be tolerated or compensated for. For example, one attempt to address this problem involves muting the comparators to prevent comparator flip while the latch circuit is latched and the output is set. The comparators may be set to a predetermined value at a given time during the latch setting interval. In this way, the comparators do not change their output value and feed-through to the latch circuit while it is latched. However, this solution effectively disables the comparators from the time the comparators are set to their predetermined value until the latch circuit is released or unlatched. During this time the comparators will not sense changes in the input signal. A device and method for reducing feed-through in the latch circuit without affecting other components in the quantizing stage of the sub-ranging ADC are desired.